G01-Screen-Gameplay

G02-Screen-Menu

G02-Screen-Stats

G02-Screen-Typing

G03-Screen-Gameplay

G03-Screen-Win

G04-Screen-Menu

G04-Screen-Question

G04-Screen-Results

G05-Screen-Main

G05-Screen-RPN

G06-Screen-Game-Over

G06-Screen-Gameplay

G07-Screen-Main

G07-Screen-Steps

G08-Screen-Translator

Git-Commit-Message-Meme

L01-Babbage-Difference-Engine

L01-CPU-Die-Shot

L01-D-Flip-Flop

L01-D-Flip-Flop-Truth-Table

L01-Domino-Computing

L01-ENIAC-Operators

L01-ENIAC-Vacuum-Tube-Panel

L01-Full-Adder

L01-Gate-AND

L01-Gate-NAND

L01-Gate-NOT

L01-Gate-OR

L01-Half-Adder

L01-Leibniz-Calculator

L01-Marble-Computer

L01-Ripple-Carry-Adder-8bit

L01-Transistor-As-Switch

L01-Transistor-Diagram-Symbol

L01-Transistor-Microscopic

L01-Transistors-Various-Sizes

L01-Vacuum-Tubes-Collection

L01-WaterSim-AND-Gate

L01-WaterSim-Flow-Off

L01-WaterSim-Flow-On

L01-WaterSim-OR-Gate

L01-WaterSim-Valve-Off

L01-WaterSim-Valve-On

L02-8bit-Components

L02-ALU-Block-Diagram

L02-Automata-Theory-Hierarchy

L02-Binary-Decoder-Circuit

L02-Binary-Decoder-Example-2

L02-Byte-8-Bits

L02-Clock-Signal-Waveform

L02-Combinational-vs-Sequential

L02-D-Latch-NAND-Circuit

L02-Hex-Binary-Decimal-Table

L02-Instruction-Decoder-ALU

L02-Latch-Write-Enable

L02-NandGame-1bit-Register

L02-NandGame-4bit-Register

L02-NandGame-D-Flipflop

L02-NandGame-D-Flipflop-Store

L02-NandGame-D-Latch-Circuit

L02-OR-Gate-With-Feedback

L02-SR-Latch-Invalid-State

L02-SR-Latch-SET-RESET

L02-TC-4bit-Adder

L02-TC-Full-Adder

L02-TC-Half-Adder

L02-Twos-Complement-NEG-Example

L02-Twos-Complement-Wheel

L03-8086-Registers-Basic

L03-8086-Registers-Full

L03-8086-Segment-Overlap

L03-Address-Space-Formula

L03-AFD-Data-Segment

L03-AFD-Registers-View

L03-AFD-Segments-Annotated

L03-Binary-Decoder

L03-CPU-ALU-Decoder

L03-Digital-Simulator-CPU

L03-FLAGS-Register

L03-Hex-Binary-Conversion

L03-Hex-counter

L03-Instruction-Encoding

L03-Instruction-Types-Gates

L03-Intel-8086-Chip

L03-Memory-Cell-Read

L03-Memory-Cell-Tristate

L03-Memory-Grid-Latches

L03-Memory-Grid-Selected

L03-Memory-With-Decoder

L03-RAM-Abstraction

L03-RAM-Complete

L03-Segment-Calc-Example1

L03-Segment-Calc-Example2

L03-Segment-Offset-Formula

L03-SRAM-vs-DRAM

L03-x64-Register-Layout

L03-x86-32bit-Registers

L04-Conditional-Jump-Table

L04-FLAGS-Register-Layout

L04-Intel-8086-Chip

L04-x86-Opcode-Table

L05-2D-Array-Memory-Layout

L05-Big-Endian-vs-Little-Endian

L05-CPU-View-Annotated

L05-Decimal-To-Binary-Conversion

L05-Endianness-Memory-Layout

L05-Push-Pop-Equivalence

L05-Real-Mode-Memory-Addressing

L05-Stack-Frame-Diagram

L05-Stack-Operations-Visual

L05-Stack-Push-Pop-Steps

L06-Apple-M3-Ultra-Die

L06-Better-Call-SAL

L06-Cache-Hierarchy

L06-Clock-Signal

L06-DRAM-Read-Timing

L06-Fetch-Decode-Execute

L06-Harvard-Architecture

L06-IC-7408-AND-Gate

L06-Memory-Hierarchy-Pyramid

L06-Moores-Law-Original-Graph

L06-Motherboard-Layout

L06-ROL-Rotate-Left

L06-ROR-Rotate-Right

L06-SAR-Shift-Arithmetic-Right

L06-Shift-Rotate-Summary-Table

L06-SHL-Shift-Left

L06-SHR-Shift-Right

L06-System-Bus-Diagram

L06-TMS1000-Chip

L06-Transistor-Count-Chart

L06-Von-Neumann-Architecture

L06-x86-Opcode-Map

L07-BIOS-Chip-Photo

L07-Boot-Sequence-Timeline

L07-DOS-Hello-World-INT21h

L07-Hardware-Interrupts-Diagram

L07-INT-IRET-After

L07-INT-IRET-Before

L07-INT-IRET-During

L07-IVT-Memory-Dump-TD

L07-IVT-Memory-Layout

L07-IVT-Structure

L07-Kernel-Architecture

L07-MBR-Hex-Dump

L07-Protection-Rings

L07-Reset-Vector-TD

L07-Virtual-Memory-Diagram

L08-ASM-1D-Array

L08-ASM-2D-Array-Access

L08-ASM-2D-Array-Declare

L08-ASM-LinkedList-Define

L08-ASM-LinkedList-Init

L08-ASM-LinkedList-Traverse

L08-ASM-Read-Scancode

L08-ASM-Set-LEDs

L08-ASM-StringArray-Data

L08-ASM-StringArray-Init

L08-ASM-StringArray-Print

L08-ASM-Struct-Annotated

L08-ASM-Struct-Define

L08-Cache-Bandwidth-Latency

L08-Cache-Hierarchy-Single

L08-Cache-Multicore

L08-CPU-Bus-Diagram

L08-CPU-Bus-IO-Highlight

L08-DOS-StringArray-Output

L08-IO-Port-Address-List

L08-Keyboard-Commands-Full

L08-Keyboard-Commands-Table

L08-Keyboard-Controller-Block

L08-Keyboard-Matrix-Block

L08-Mechanical-Keyboard

L08-Memory-Hierarchy-Detailed

L08-Memory-Hierarchy-Pyramid

L08-Memory-Speed-Pyramid

L08-Motherboard-Closeup

L08-Network-Switch

L08-Paging-Address-Translation

L08-Scancode-Table

L08-Virtual-Memory-Mapping

L09-CISC-RISC-Convergence

L09-CISC-RISC-Convergence-UK

L09-Counter-Machine-ISA

L09-Counter-Machine-ISA-UK

L09-Direct-vs-Indirect-Addressing

L09-Direct-vs-Indirect-Addressing-UK

L09-Flynn-MIMD

L09-Flynn-MISD

L09-Flynn-SIMD

L09-Flynn-SISD

L09-Flynn-Taxonomy-Table

L09-ISA-Accumulator-Based

L09-ISA-Boundary

L09-ISA-Boundary-UK

L09-ISA-Classification-Axes

L09-ISA-Classification-Axes-UK

L09-ISA-Implementations

L09-ISA-Implementations-UK

L09-ISA-Register-Memory-And-Register-Register

L09-ISA-Stack-Based

L09-Lecture-Outline

L09-Lecture-Outline-UK

L09-Memory-Memory-Architecture

L09-Memory-Memory-Architecture-UK

L09-Models-of-Computation-Progression

L09-Models-of-Computation-Progression-UK

L09-RAM-Machine-Architecture

L09-RAM-vs-RASP

L09-RAM-vs-RASP-UK

L09-RASP-Machine-Architecture

L09-Turing-Machine

L09-Turing-Machine-UK

L09-VLIW-Instruction-Word

L09-VLIW-Instruction-Word-UK

L10-ASIC-Crypto-Mining-Rig

L10-Bitcoin-Mining-Difficulty

L10-CPU-Closeup

L10-CPU-vs-GPU-Cores

L10-DSP-ADC-DAC-Diagram

L10-DSP-Chip-Vintage

L10-DSP-Harvard-Architecture

L10-DSP-Instructions-Table

L10-DSP-TMS320-Chip

L10-FPGA-Structure

L10-FPGA-Xilinx-Spartan6

L10-GPU-Intel-Flex-Series

L10-GPU-NVIDIA-SM-Architecture

L10-GPU-Thread-Execution

L10-IBM-NorthPole-Board

L10-Intel-Loihi-Architecture

L10-Neuromorphic-Brain-Circuit

L10-Neuromorphic-Brain-To-Chip

L10-Quantum-Computer

L10-Quantum-Qubits-Text

L10-Tesla-DOJO-D1-Die

L10-Tesla-DOJO-Stack

L10-Tesla-DOJO-Training-Tile

L10-TPU-Google

L10-VLIW-Execution-Diagram

L10-VLIW-Pipeline

L10-VLIW-Transmeta-Crusoe

L11-Address-Decomposition

L11-Address-Decomposition-ENG

L11-AMAT-Multilevel

L11-AMAT-Multilevel-ENG

L11-Associativity-Comparison

L11-Associativity-Comparison-ENG

L11-Cache-Line-Anatomy

L11-Cache-Line-Anatomy-ENG

L11-Cache-Topology

L11-Cache-Topology-ENG

L11-Coherence-Problem

L11-Coherence-Problem-ENG

L11-Direct-Mapped-Cache

L11-Direct-Mapped-Cache-ENG

L11-False-Sharing

L11-False-Sharing-ENG

L11-Matrix-Access-Patterns

L11-Matrix-Access-Patterns-ENG

L11-MESI-State-Diagram

L11-MESI-State-Diagram-ENG

L11-Processor-Memory-Gap

L11-Processor-Memory-Gap-ENG

L11-Write-Policies

L11-Write-Policies-ENG

L12-Address-Translation

L12-Address-Translation-ENG

L12-Clock-Algorithm

L12-Clock-Algorithm-ENG

L12-Four-Level-Page-Table

L12-Four-Level-Page-Table-ENG

L12-Full-Memory-Access-Path

L12-Full-Memory-Access-Path-ENG

L12-Page-Fault-Handling

L12-Page-Fault-Handling-ENG

L12-Page-Table-Entry

L12-Page-Table-Entry-ENG

L12-TLB-Lookup-Flow

L12-TLB-Lookup-Flow-ENG

L12-Two-Level-Page-Table

L12-Two-Level-Page-Table-ENG

L12-Virtual-Address-Space

L12-Virtual-Address-Space-ENG

L12-Virtual-Physical-Mapping

L12-Virtual-Physical-Mapping-ENG

L13-Denormalized-FP-Formula

L13-Division-By-Zero-Formula

L13-Example-Conversion-Bits

L13-FP-Bit-Layout

L13-FP-Precision-Meme

L13-IEEE754-Formats-Table

L13-Intel-80387-Chip

L13-JS-Console-FP-Demo

L13-Max-Min-FP-Bit-Diagrams

L13-NaN-Bit-Layout

L13-Normalized-Binary-Examples

L13-Normalized-FP-Formula

L13-Overflow-Underflow-Number-Line

L13-Pi-Digits

L13-Pi-Error-Calculation

L13-X87-FPU-Registers

L14-Backend-Utilization

L14-Backend-Utilization-ENG

L14-Branch-Predictor-2bit

L14-Branch-Predictor-2bit-ENG

L14-Coffee-Shop

L14-Coffee-Shop-ENG

L14-Forwarding-Bypass

L14-Forwarding-Bypass-ENG

L14-Instruction-Lifecycle

L14-Instruction-Lifecycle-ENG

L14-M1-Block-Diagram

L14-M1-Block-Diagram-ENG

L14-Photo-Clock-Speed-Chart

L14-Photo-IBM-360-91

L14-Photo-Itanium-Die

L14-Photo-M1-Die

L14-Photo-Meltdown-Logo

L14-Photo-Pentium4-Die

L14-Photo-Spectre-Logo

L14-Pipeline-Hardware

L14-Pipeline-Hardware-ENG

L14-Register-Renaming

L14-Register-Renaming-ENG

L14-Running-Example-Forwarding

L14-Running-Example-Forwarding-ENG

L14-Running-Example-OoO

L14-Running-Example-OoO-ENG

L14-Running-Example-Pipelined

L14-Running-Example-Pipelined-ENG

L14-Running-Example-Sequential

L14-Running-Example-Sequential-ENG

L14-Running-Example-Superscalar

L14-Running-Example-Superscalar-ENG

L14-Single-Cycle-Waste

L14-Single-Cycle-Waste-ENG

L14-SMT-Sharing

L14-SMT-Sharing-ENG

L14-Spectre-Cache-Sidechannel

L14-Spectre-Cache-Sidechannel-ENG

L14-Superscalar-Hardware

L14-Superscalar-Hardware-ENG

L14-Tomasulo-CDB

L14-Tomasulo-CDB-ENG

L15-3D-Die-Stacking-Concept

L15-Amdahls-Law

L15-Amdahls-Law-ENG

L15-bigLITTLE-Cluster-Switching

L15-bigLITTLE-Cortex-A57-A53

L15-bigLITTLE-Global-Task-Scheduling

L15-bigLITTLE-In-Kernel-Switcher

L15-Chiplet-Package

L15-Chiplet-Package-ENG

L15-CMOS-Power-Breakdown

L15-CMOS-Power-Breakdown-ENG

L15-Course-Arc

L15-Course-Arc-ENG

L15-CPU-Clock-Core-Count

L15-Dark-Silicon-Chip

L15-Dark-Silicon-Chip-ENG

L15-Data-Center-Cold-Aisle

L15-Data-Center-Racks

L15-DVFS-Curve

L15-DVFS-Curve-ENG

L15-Future-Tech-Landscape

L15-Future-Tech-Landscape-ENG

L15-Gustafsons-Law

L15-HBM-Fiji-GPU-Package

L15-HBM-Schematic

L15-Heterogeneous-SoC

L15-Heterogeneous-SoC-ENG

L15-Moores-Law-Transistor-Count

L15-Optimizing-Different-Parts

L15-Optimizing-Different-Parts-ENG

L15-Power-Gating-vs-Clock-Gating

L15-Power-Gating-vs-Clock-Gating-ENG

L15-PUE-Breakdown

L15-PUE-Breakdown-ENG

L15-Race-to-Idle-vs-Slow-Steady

L15-Race-to-Idle-vs-Slow-Steady-ENG

L15-Scaling-Laws-Timeline

L15-Scaling-Laws-Timeline-ENG

Lab01-DigiLoSim-Download

Lab01-GitHub-Register

Lab09-Arg-Parser-FSM

loom-logo

R01-Screen-GameOver

R01-Screen-Gameplay

R02-Screen-GameOver

R02-Screen-Gameplay

R03-Screen-Editing

R03-Screen-SaveDialog

R04-Screen-GameOver

R04-Screen-Gameplay

R05-Screen-Gameplay

R05-Screen-Install

R06-Screen-Gameplay

R06-Screen-Win

R07-Screen-Check

R07-Screen-Checkmate

R07-Screen-Gameplay

UKMA-logo

Y01-Screen-GameOver

Y01-Screen-Gameplay

Y02-Screen-Editor

Y02-Screen-Simulation

Y03-Screen-Gameover

Y03-Screen-Gameplay

Y04-Screen-Gameplay

Y04-Screen-Win

Y05-Screen-GameOver

Y05-Screen-Gameplay

Y06-Screen-Complete

Y06-Screen-Gameplay

Y07-Screen-Gameplay

Y07-Screen-Win

Y08-Screen-GameOver

Y08-Screen-Gameplay

Y08-Screen-Placement

Y09-Screen-Gameover

Y09-Screen-Gameplay

Y10-Screen-GameOver

Y10-Screen-Gameplay

Y11-Screen-Gameover

Y11-Screen-Gameplay

Y12-Screen-Gameover

Y12-Screen-Gameplay

Y12-Screen-Multijump

Y13-Screen-Evolution

Y14-Screen-Editor

Y14-Screen-Viewer

Y15-Screen-Visualization

Y16-Screen-Playback

Y17-Screen-Generation

Y17-Screen-Solved

Y18-Screen-Prompt

Y18-Screen-Results

Y19-Screen-Form

Y19-Screen-List

Y20-Screen-Login

Y20-Screen-Main

Y20-Screen-Reveal

Y21-Screen-Editor

Y21-Screen-Tools

Y22-Screen-Viewer

Y22-Screen-Zoomed

Y23-Screen-DayView

Y23-Screen-Monthly

Y24-Screen-Gameplay

Y24-Screen-Results

L01-Prep

L02-Prep

L03-Prep

L04-Prep

L05-Prep

L06-Prep

L07-Prep

L08-Prep

L09-Prep

L10-Prep

L11-Prep

L12-Prep

L13-Prep

L14-Prep

L15-Prep

Preparation-Guide

demo_key

demo_variant

Methodology

practice

README

Contest

Lab01

Lab02

Lab03

Lab03-Setup

Lab04

Lab04-TD

Lab05

Lab06

Lab07

Lab08

Lab09

Lab11

Lab12

Lab13

Lab14

Project

Project-Defense

Project-Report

L01-NOTES. Фізика обчислень

L01. Фізика обчислень

L02-Notes. Від вентилів до АЛП

L02. Від вентилів до АЛП

L03-NOTES. Архітектура x86 — регістри та пам'ять

L03-Segments. Сегментна адресація — покрокове пояснення

L03. Архітектура x86 — регістри та пам'ять

L04-NOTES. Архітектура x86 — основні типи інструкцій

L04. Архітектура x86 — основні типи інструкцій

L05-NOTES. Організація програми — стек і процедури

L05-Stack-Frames. Стекові фрейми — покрокове пояснення

L05. Організація програми — стек і процедури

L06-NOTES. Системна архітектура

L06. Системна архітектура

L07-NOTES. Переривання та взаємодія з ОС

L07. Переривання та взаємодія з ОС

L08-NOTES. Пристрої. Ієрархія пам'яті. Структури даних на низькому рівні

L08. Пристрої. Ієрархія пам'яті. Структури даних на низькому рівні

L09-NOTES. Проєктування ISA та моделі обчислень

L09. Проєктування ISA та моделі обчислень

L10-NOTES. Огляд сучасних архітектур

L10. Огляд сучасних архітектур

L11-NOTES. Ієрархія пам'яті та продуктивність

L11. Ієрархія пам'яті та продуктивність

L12-NOTES. Віртуальна пам'ять поглиблено

L12. Віртуальна пам'ять поглиблено

L13-NOTES. Арифметика з рухомою комою

L13. Арифметика з рухомою комою

L14-NOTES. Паралелізм на рівні інструкцій та потоків

L14. Паралелізм на рівні інструкцій та потоків

L15-NOTES. Енергоефективність, обмеження та майбутні тренди

L15. Енергоефективність, обмеження та майбутні тренди

demo_key

demo_variant

README

Консультація - 2026-01-17

Консультація - 2026-01-24

Консультація - 2026-01-31

Консультація - 2026-02-07

Консультація - 2026-02-14

Консультація - 2026-02-21

Консультація - 2026-02-28

Консультація - 2026-03-07

Консультація - 2026-03-14

Консультація - 2026-03-21

Консультація - 2026-03-28

Консультація - 2026-04-04

Консультація - 2026-04-11

Консультація - 2026-04-18

G01-Tic-Tac-Toe

G02-Typing-Speed-Trainer

G03-Memory-Card-Game

G04-Quiz-Trivia-Game

G05-Calculator-With-History

G06-Hangman

G07-Number-Base-Converter

G08-Morse-Code-Translator

R01-Tetris

R02-Breakout

R03-Mini-Text-Editor

R04-Pac-Man

R05-TSR-Hotkey-Utility

R06-Lights-Out

R07-Chess

README

Y01-Snake

Y02-Conways-Game-of-Life

Y03-Minesweeper

Y04-Connect-Four

Y05-2048

Y06-Sokoban

Y07-15-Puzzle

Y08-Battleship

Y09-Othello-Reversi

Y10-Space-Invaders

Y11-Frogger

Y12-Checkers

Y13-Wolfram-Cellular-Automaton

Y14-Hex-Viewer-Editor

Y15-Sorting-Visualizer

Y16-Music-Player

Y17-Maze-Generator-Solver

Y18-Mini-Grep

Y19-Address-Book

Y20-Password-Manager

Y21-ASCII-Art-Editor

Y22-Mandelbrot-Viewer

Y23-Calendar-Planner

Y24-Rhythm-Game